1. Field of Invention
This invention relates to mixed-signal converters of the current steering type, and more particularly, to sigma-delta digital-to-analog converter that employs a continuous-time current-to-voltage circuit in the output stage.
2. Discussion of Prior Art
Current steering topology is a commonly used approach in industry to realize digital-to-analog converters. Due to its simplicity and flexibility, this topology is employed in a large combination of high speed or high resolution applications. FIG. 1 illustrates a typical implementation of a 16-level thermometer-code current steering DAC 100. The DAC consists of a bank of current steering cells 102, 104, 106, and 108, amplifier 110, a pair of feedback resistors 112 and 114, and in some cases a pair of capacitors, C1 116 and C2 118. Capacitors 116 and 118 effectively slow down the step output waveform to help reduce the amplifier slew rate requirement. The control bits and their complementary version are, in the simplest form, the Q and QB outputs of a D-flip flop array. The inputs of these D-flip flops are the digital DAC codes. The circuit operation is quite simple in that the digital codes control how many cells will be directed to the appropriate summing junction of the amplifier. A clock which defines the conversion rate of the DAC is used to synchronize all output transitions of the control bits via the D-flip flops.
Sigma-delta digital-to-analog converters (DACs) provide for a means to achieve high resolution and low distortion at a relatively low cost compared to traditional Nyquist converters. In the past, there have been many realizations of these very high resolution DACs which used current steering topology in their output stage. Examples of such implementations can be found in the paper by Douglas Mercer titled “A Low Power Current Steering Digital to Analog Converter in 0.18 Micron CMOS” and in the paper by Adams et al. titled “A 113-dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling”.
The above-mentioned paper by Douglas Mercer teaches a plurality of circuit techniques that address the DC and AC distortion performance of a low-power current steering Digital-to-Analog Converter design. Mercer's techniques resulted in AC distortion equal to high power DACs with dissipation as much as 10 times larger.
The above-mentioned paper by Adams et al. teaches a sigma-delta digital-to-analog converter implemented in a 0.6 micron CMOS and using a 6-bit modulator together with a segmented noise-shaped scrambling scheme to achieve 113-dB A-weighted dynamic range over a 20-kHz bandwidth. Adams' output stage uses a dual return-to-zero circuit that eliminates errors caused by inter-symbol interference (ISI).
FIG. 2 illustrates a block diagram of a prior art audio band multi-bit sigma-delta DAC 200 employing current steering output stage. The converter consists of an up-sampler 202 to up-sample the digital input to the designed operating frequency of the system, typically, at 128 times the input sample rate Fs (Fs=48 kHz). The output of up-sampler 202 is input into digital filter 204, which filters the images resulting from the up-sampling process. A sigma-delta modulator 206 then reduces the output word-width of the digital filter, typically from 24 bit, down to a more manageable size, typically 4 to 6 bit. This modulation essentially trades off the out-of-band noise for a smaller word-width by pushing the truncation errors into the higher unused frequency region. Binary-to-thermometer encoder 208 is then used to encode the binary weighted data into thermometer code data. The output of binary-to-thermometer encoder 208 is a set of 2N elements, where N is the designed word-width of the modulator output. Each element of this set will then drive a current cell in the bank of current cells. To ensure the linearity of this bank of current cells, a data selection logic (also called shuffler or scrambler) 210 is then used to select a subset of the 2N elements according to the digital code from the thermometer encoder output. The output voltage is produced by converting the sum of the selected current cells into voltage via a current-to-voltage (I-to-V) converter. The output of element shuffler 210 is fed into thermometer-code DAC 212. To filter out the out-of-band noise, a post-analog filter (not shown) is typically used.
A very well understood problem associated with current steering DAC is the inter-symbol-interference (ISI). This ISI problem is the result of un-equal rise and fall time in the waveform of the current pulse delivered to the output by each current cell. Consequently, the present value of the DAC output depends on its previous value. The net effect is a major degradation in the total harmonic distortion (THD) and noise performance of the DAC.
Prior art techniques such as the return-to-zero (RTZ) technique, was used to minimize the effect of ISI. The principle of RTZ is illustrated in FIG. 3. RTZ forces each current cell to turn off for a duration, typically half of the clock period. Hence, the output of the DAC always starts from zero at the beginning of each clock period. The ISI is thus completely removed. The major drawbacks of this technique include a high slew rate, bandwidth requirement and high power consumption in the amplifier; additional high frequency content introduced as the result of returning to the zero state. Further, the subsequent filtering stage of the DAC will have to be very linear, a challenging task in its own, to avoid distortions that may cause by such a high dynamic output from the DAC.
FIG. 4 illustrates the dual RTZ technique which sums the output of two RTZ waveforms which are delayed by half of the clock period from each other. The previously described paper to Adams et al. and the U.S. Pat. No. 6,061,010 titled, “Dual return-to-zero pulse encoding in a DAC output stage” teaches for such a dual RTZ technique. By the principle of superposition theorem, the sum of two ISI-free waveforms must yield an ISI free output. The major draw back of this technique is the addition of the second current bank used to create the delayed RTZ waveform. This addition doubles the silicon area, consumes twice the amount of power and complicates the clock scheme and data synchronization between the digital and analog interface of the DAC.
Prior art low ISI gate drive circuitries can help reducing the effects of ISI by ensuring that the current cell always sees the same symmetrical disturbance at its drain when the control bits make a transition from 1 to 0, and from 0 to 1. It has been known that this type of circuit cannot eliminate ISI completely. Further, when the logic makes a transition, it draws a large current spike from the supply making it not suitable for low power consumption implementation.
Whatever the precise merits, features, and advantages of the above cited references and techniques, none of them achieves or fulfills the purposes of the present invention.